Embodiments of the present embodiments relate to an isolated semiconductor controlled rectifier (SCR) circuit for electrostatic discharge (ESD) protection. A preferred embodiment of the circuit is intended for use at input, output, or input-output terminals having a negative operating voltage with respect to GND or VSS, but the circuit may also be used between power supply terminals such as VDD and GND or VSS terminals of an integrated circuit.
Referring to FIGS. 1-3, there is an ESD protection circuit of the prior art that is similar to those disclosed by Ker et al. in U.S. Pat. No. 6,765,771. The plan view of FIG. 1 illustrates a dual semiconductor controlled rectifier formed on p-type substrate (PSUB) 102 and surrounded by n-type well (NWELL) 100. The PSUB layer 102 is electrically connected to P+ region 112. The dual SCRs are formed symmetrically above and below P+ region 112, so only the lower SCR will be described in detail. Here and in the following discussion the same reference numerals are used to identify the same or similar circuit elements in the various drawing figures. N+ region 114 is the cathode of the lower SCR and is formed adjacent P+ region 112 within p-type well region 104. P+ region 108 is formed within NWELL 100 and serves as an anode for the lower SCR. N+ region 106 is electrically connected to NWELL 100. Gate region 110 is formed over a boundary between NWELL 100 and PSUB 102. Gate region 110, P+ anode 108, and N+ region 106 are electrically connected to reference terminal 122, which is preferably GND or VSS. P+ region 112 and N+ region 114 are electrically connected to terminal 120, which is preferably an input, output, or input-output terminal to be protected.
Referring next to FIG. 2, there is a cross sectional diagram of the lower SCR along the plane A-A′ as indicated by the line in FIG. 1. The SCR is formed on P-type substrate (PSUB) 200. N-type buried layer (NBL) 101 is formed in PSUB 200 below the surface by ion implantation. Taken together n-type well (NWELL) 100 and NBL 101 form an isolated P-type region (PSUB) 102. The lower SCR includes P+ anode 108 formed in NWELL 100 and N+ cathode 114 formed in p-type well region 104. Active P+ regions 112 and 108, N+ regions 114 and 106, and the channel region below gate 110 are separated by shallow trench isolation (STI) regions 124.
Turning now to FIG. 3, there is a simplified diagram of the SCR of FIG. 2 showing individual bipolar transistors. Shallow trench isolation (STI) regions are omitted for clarity. The lower SCR of FIG. 2 comprises a vertical SCR and a horizontal SCR. The vertical SCR includes PNP transistor 304 and NPN transistor 306 and forms a vertical current path from P+ anode 108 to NBL 101 via NWELL 100 and back to N+ cathode 114 via PSUB 102. The horizontal SCR includes PNP transistor 300 and NPN transistor 302 and forms a horizontal current path directly from P+ anode 108 to N+ cathode 114. Parasitic resistor 301 is a base-emitter shunt resistor for PNP transistor 300. Parasitic resistor 303 is a base-emitter shunt resistor for NPN transistors 302 and 306.
Several problems arise with operation of the SCR of FIGS. 1-3 that limit operating voltage, gain of the SCR, and introduce reliability problems as will become apparent in the following discussions. Various embodiments of the present invention are directed to solving these problems and improving operation of the SCR without increasing process complexity.